منابع مشابه
Low Power Clock Network Design
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanc...
متن کاملNavigating Register Placement for Low Power Clock Network Design
In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate register placement to locations that enable further less clock routing wirelength. To minimize adverse i...
متن کاملLow Power Clock Gated Sequential Circuit Design
Reducing Power dissipation is one of the crucial problems in today’s scenario. So this dissipation has become a bottleneck in the design of high speed synchronous systems which are operating at high frequency. Clock signals have been a great source of Power. Design can be made on the basis of Clock gating approach to reduce the consumption of clock’s signal switching power which is the foremost...
متن کاملNavigating Register Placement for Low Power Clock Network
With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength an...
متن کاملGated clock routing for low-power microprocessor design
This paper presents a zero-skew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the switched capacitance of the clock tree. We construct a clock tree topology based on the locations...
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ژورنال
عنوان ژورنال: Journal of Low Power Electronics and Applications
سال: 2011
ISSN: 2079-9268
DOI: 10.3390/jlpea1010219